1. Field of the Invention
The invention generally relates to capacitor designs and in particular relates to a capacitor cell structure that provides complete shielding from adjacent cells on all sides of the structure.
2. Discussion of Related Art
Capacitors are electronic circuits that store electrical charge and are generally designed to apply a potential across two electrodes separated by a dielectric layer of material. Capacitors are typically formed in semiconductor integrated circuits by depositing and etching layers of polysilicon and metal conductive terminals (electrodes) and a gate oxide material used as the dielectric layer. A typical capacitor having two such electrodes may be referred to as a 2-sided capacitor. A potential applied between the two electrodes and across the dielectric is substantially retained by the capacitor.
Such semiconductor structures of polysilicon and oxide tend to be highly non-linear in their response to potential differences unless a bias voltage is maintained across the dielectric oxide material. Metal-metal capacitors are formed of two metal conductive surfaces separated by a dielectric material layer. These structures tend to respond in a more linear fashion as compared to semiconductor capacitor structures and hence are often referred to as linear capacitors.
Electronic devices including capacitors are susceptible to “crosstalk” interference from other nearby devices and interconnect signal paths (i.e., conductive signal routes and buses within the same integrated circuit design in close proximity to the capacitor or other circuit). Crosstalk interference is generated by inductance or leakage current flow between a first signal path or circuit and a second signal path or circuit.
In dense integrated circuit designs, it is a particular problem to reduce such crosstalk interference. The dense integration of modern integrated circuit dies places circuits and interconnecting signal paths in very close proximity. To reduce the potential for crosstalk interference in capacitor designs within integrated circuit dies it is common to enforce spacing rules in the circuit die layout to separate a capacitor circuit from surrounding signal paths and circuits. Some prior designs have also provided a shielding layer on top and bottom of the stack of alternating metal or electrode layers. But the shielding layers as presently practiced are not interconnected (i.e., by vias) and do not substantially enclose the signal metal conductive layers (i.e., at the sides of the conductive signal layers). Such designs do not fully shield the metal conductive layers from nearby capacitors and signal paths. Further, the enforced spacing between a capacitor and adjacent signal paths and circuits increase the circuit die size.
It is evident from the above discussion that it remains an ongoing problem to reduce crosstalk interference in integrated circuit capacitor designs.